Elements of this invention are based upon properties of a serial link. Various serial links for transmitting data and clock signals are well known.
One conventional serial link, used primarily for high-speed transmission of video data from a host processor (e.g., a personal computer) to a monitor, is known as a transition minimized differential signaling (“TMDS”) interface (sometimes referred to as a TMDS link). The characteristics of a TMDS link include the following:                1. video data are encoded and then transmitted as encoded words (each 8-bit word of digital video data is converted to an encoded 10-bit word before transmission);                    a. the encoding determines a set of “in-band” words and a set of “out-of-band” words (the encoder can generate only “in-band” words in response to video data, although it can generate “out-of-band” words in response to control or sync signals. Each in-band word is an encoded word resulting from encoding of one input video data word. All words transmitted over the link that are not in-band words are “out-of-band” words);            b. the encoding of video data is performed such that the in-band words are transition minimized (a sequence of in-band words has a reduced or minimized number of transitions);            c. the encoding of video data is performed such that the in-band words are DC balanced (the encoding prevents each transmitted voltage waveform that is employed to transmit a sequence of in-band words from deviating by more than a predetermined threshold value from a reference potential. Specifically, the tenth bit of each “in-band” word indicates whether eight of the other nine bits thereof have been inverted during the encoding process to correct for an imbalance between running counts of ones and zeroes in the stream of previously encoded data bits);                        2. the encoded video data and a video clock signal are transmitted as differential signals (the video clock and encoded video data are transmitted as differential signals over conductor pairs);        3. three conductor pairs are employed to transmit the encoded video, and a fourth conductor pair is employed to transmit the video clock signal; and        4. signal transmission occurs in one direction, from a transmitter (typically associated with a desktop or portable computer, or other host) to a receiver (typically an element of a monitor or other display device).        
A use of the TMDS serial link is the “Digital Visual Interface” interface (“DVI” link) adopted by the Digital Display Working Group. A transmitter that complies with the Digital Visual Interface standard, Revision 1.0, Apr. 2, 1999 (the “DVI specification”) will sometimes be referred to herein as a “DVI” transmitter, a receiver that complies with the DVI specification will sometimes be referred to herein as a “DVI” receiver, and a system that complies with the DVI specification will sometimes be referred to herein as a “DVI” system.
A DVI system, and aspects of the DVI specification, will be described with reference to FIG. 1. A DVI system can be implemented to include two TMDS links (which share a common conductor pair for transmitting a video clock signal) or one TMDS link, as well as additional control lines between the transmitter and receiver. The DVI system of FIG. 1 includes DVI transmitter 1, DVI receiver 3, and the following conductors between the transmitter and receiver: four conductor pairs (Channel 0, Channel 1, and Channel 2 for video data, and Channel C for a video clock signal), Display Data Channel (“DDC”) lines for bidirectional communication between the transmitter and a monitor associated with the receiver in accordance with the conventional Display Data Channel standard (the Video Electronics Standard Association's “Display Data Channel Standard,” Version 2, Rev. 0, dated Apr. 9, 1996), a Hot Plug Detect (HPD) line (on which the monitor transmits a signal that enables a processor associated with the transmitter to identify the monitor's presence), Analog lines (for transmitting analog video to the receiver), and Power lines (for providing DC power to the receiver and a monitor associated with the receiver). The Display Data Channel standard specifies a protocol for bidirectional communication between a transmitter and a monitor associated with a receiver, including transmission by the monitor of an Extended Display Identification (“EDID”) message that specifies various characteristics of the monitor, and transmission by the transmitter of control signals for the monitor. DVI transmitter 1 includes three identical encoder/serializer units (units 2, 4, and 6) and additional circuitry (not shown). DVI receiver 3 includes three identical recovery/decoder units (units 8, 10, and 12) and inter-channel alignment circuitry 14 connected as shown, and additional circuitry (not shown). Units 2, 4, and 6, perform TMDS encoding on the data to be transmitted, and units 8, 10, and 12 decode the TMDS-encoded data after transmission.
As shown in FIG. 1, circuit 2 encodes the data to be transmitted over Channel 0, and serializes the encoded bits. Similarly, circuit 4 encodes the data to be transmitted over Channel 1 (and serializes the encoded bits), and circuit 6 encodes the data to bc transmitted over Channel 2 (and serializes the encoded bits). Each of circuits 2, 4, and 6 responds to a control signal (an active high binary control signal referred to as a “data enable” or “DE” signal) by selectively encoding either digital video words (in response to DE having a high value) or a control or synchronization signal pair (in response to DE having a low value). Each of encoders 2, 4, and 6 receives a different pair of control or synchronization signals: encoder 2 receives horizontal and vertical synchronization signals (HSYNC and VSYNC); encoder 4 receives control bits CTL0 and CTL1; and encoder 6 receives control bits CTL2 and CTL3. Thus, each of encoders 2, 4, and 6 generates in-band words indicative of video data (in response to DE having a high value), encoder 2 generates out-of-band words indicative of the values of HSYNC and VSYNC (in response to DE having a low value), encoder 4 generates out-of-band words indicative of the values of CTL0 and CTL1 (in response to DE having a low value), and encoder 6 generates out-of-band words indicative of the values of CTL2 and CTL3 (in response to DE having a low value). In response to DE having a low value, each of encoders 4 and 6 generates one of four specific out-of-band words indicative of the values 00, 01, 10, or 1, respectively, of control bits CTL0 and CTL1 (or CTL2 and CTL3).
In operation of the FIG. 1 system, cable 23 (comprising connectors 20 and 21 and conductors 22) is connected between transmitter 1 and receiver 3. Conductors 22 include a conductor pair for transmitting serialized data over Channel 0 from encoder 2 to decoder 8, a conductor pair for transmitting serialized data over Channel 1 from encoder 4 to decoder 10, a conductor pair for transmitting serialized data over Channel 2 from encoder 6 to decoder 12, and a conductor pair for transmitting a video clock over Channel C from transmitter 1 to receiver 3. Conductors 22 also include wires for the DDC channel (which can be used for bidirectional 12C communication between transmitter 1 and receiver 3), a Hot Plug Detect (HPD) line, “Analog” lines for analog video transmission from transmitter 1 to receiver 3, and “Tower” lines for provision of power from transmitter 1 to a receiver 3.
In receiver 3, the data signal received on Channel 0 is sampled in unit 8 and the samples are deserialized and decoded. The data signal received on Channel 1 is sampled in unit 10 and the samples are deserialized and decoded. The data signal received on Channel 2 is sampled in unit 12 and the samples are deserialized and decoded. The decoded samples are indicative of recovered data, control, and sync bits, and the decoded bits are asserted to inter-channel alignment circuitry 14.
Throughout the specification (including in the claims), the expression “TMDS-like encoding” of data for transmission over a serial link will be used to denote TMDS encoding and other encoding in which N-bit words of data (e.g., video data) are encoded as M-bit code words, where M is greater than N (e.g., N=8, M=10, and each 8-bit input word is encoded as a 10-bit code word before transmission); and each code word is either a “transition-minimized” code word or a “transition-maximized” code word, each transition-minimized code word having less than a predetermined number of transitions between consecutive bits thereof, and each transition-maximized code word having more than the predetermined number of transitions between consecutive bits thereof. A transition-maximized code word will sometimes be denoted herein as a “Max” word. A transition-minimized code word will sometimes be denoted herein as a “Min” word. Encoded data that have been encoded in accordance with “TMDS-like encoding” will be referred to herein as “TMDS-like encoded data.”
In a binary bit stream (e.g., a sequence of serially-transmitted binary bits indicated by a data signal), there are “runs” of consecutive “zero” bits and/or “runs” of consecutive “one” bits. The runs typically do not all have the same length. We use the expression “maximum run length” herein to denote the length of the longest run (of identical bits) in a data signal that is indicative of a binary bit sequence. For example, a stream of serially-transmitted data has a maximum run length of 7 if it has runs (of identical bits) of length 7 or less, but no run (of identical bits) of length greater than 7.
We use the expression “average run length” herein to denote the average length of all runs in a data signal that is indicative of a binary bit sequence.
Long run length causes severe inter-symbol interference (ISI) in long cable high-speed serial communication. In transmission of transition-minimized TMDS-encoded data (during active video periods), the low number of transitions results in longer run length than in transmission of transition-maximized TMDS-encoded data (during blanking intervals). Although maximum run length is controlled and limited by the DC balancing implemented by TMDS encoding, conventional TMDS encoding cannot reliably reduce ISI to acceptable levels in at least some high frequency applications (i.e., applications with high data rate) and in at least some cases in which TMDS-encoded data are transmitted over long cable interconnects.
Preferred embodiments of the present invention employ an improved version of TMDS encoding that is still compatible with legacy TMDS receivers, and reduces maximum run length (and average run length) significantly to reduce ISI, even in very high frequency applications and applications in which the encoded data are transmitted over long cables.